// First row (i=0): just pass partial product (no addition) assign P[0] = pp[0][0];
integer i, j; initial begin $monitor("Time=%0t | A=%d B=%d | Product=%d (expected %d)", $time, A, B, P, A*B); for (i = 0; i < 256; i = i + 1) begin for (j = 0; j < 256; j = j + 1) begin A = i; B = j; #10; if (P !== A*B) begin $display("ERROR: %d * %d = %d, but got %d", A, B, A*B, P); $finish; end end end $display("All tests passed."); $finish; end endmodule Running the testbench yields correct multiplication for all 65,536 input combinations. Example:
// Final row (i=7) wire [7:0] final_carry; generate for (j = 0; j < 7; j = j + 1) begin if (j == 0) ha ha_final (.a(pp[7][0]), .b(s[6][0]), .sum(s[7][j]), .carry(final_carry[j])); else fa fa_final (.a(pp[7][j]), .b(s[6][j]), .cin(final_carry[j-1]), .sum(s[7][j]), .cout(final_carry[j])); end assign s[7][7] = final_carry[6]; endgenerate 8 bit array multiplier verilog code
// Final row (row 7) -> outputs become final product bits // P[1] to P[7] come from sum[0..6] and final additions wire [7:0] final_sum; wire [7:0] final_carry;
// Row 7: full adders for all but last column generate for (j = 0; j < 7; j = j + 1) begin : final_row if (j == 0) begin ha final_ha ( .a (pp[7][0]), .b (sum[6][j]), .sum (final_sum[j]), .carry(final_carry[j]) ); end else begin fa final_fa ( .a (pp[7][j]), .b (sum[6][j-1]), .cin (final_carry[j-1]), .sum (final_sum[j]), .cout (final_carry[j]) ); end end endgenerate // First row (i=0): just pass partial product
This work implements an using structural and dataflow modeling in Verilog. 2. Multiplication Algorithm Let the multiplicand be ( A = A_7A_6...A_0 ) and multiplier be ( B = B_7B_6...B_0 ). The product ( P = A \times B ) is computed as:
// Generate partial products: pp[i][j] = A[i] & B[j] genvar i, j; generate for (i = 0; i < 8; i = i + 1) begin : pp_gen for (j = 0; j < 8; j = j + 1) begin : bit_gen assign pp[i][j] = A[i] & B[j]; end end endgenerate Multiplication Algorithm Let the multiplicand be ( A
[ P = \sum_i=0^7 (A \cdot B_i) \cdot 2^i ]
// Assign product bits assign P[1] = sum[0][0]; assign P[2] = sum[1][1]; assign P[3] = sum[2][2]; assign P[4] = sum[3][3]; assign P[5] = sum[4][4]; assign P[6] = sum[5][5]; assign P[7] = sum[6][6]; assign P[8] = final_sum[0]; assign P[9] = final_sum[1]; assign P[10] = final_sum[2]; assign P[11] = final_sum[3]; assign P[12] = final_sum[4]; assign P[13] = final_sum[5]; assign P[14] = final_sum[6]; assign P[15] = final_sum[7];
// Middle rows (i=1 to 6) genvar i; generate for (i = 1; i < 7; i = i + 1) begin // First bit of row i ha ha_i0 (.a(pp[i][0]), .b(s[i-1][0]), .sum(s[i][0]), .carry(c[i][0])); // Remaining bits for (j = 1; j < 7; j = j + 1) begin fa fa_ij (.a(pp[i][j]), .b(s[i-1][j]), .cin(c[i][j-1]), .sum(s[i][j]), .cout(c[i][j])); end // Last bit of row i assign s[i][7] = c[i][6]; end endgenerate
// Row 1: half adder at LSB, rest pass carry/sum assign sum[0][0] = pp[1][0]; assign carry[0][0] = 1'b0; // Not used